1. Field of the Invention
The invention relates to the process for providing nitrogen in a semiconductor substrate, particularly for forming an oxide region using differential oxide growth.
2. Description of the Related Art
A prevalent trend in the semiconductor industry is to increase the density of semiconductor devices formed on silicon substrates.
Programmable logic devices (PLD) are circuits which can be configured by a user to perform logic functions or serve as memory arrays. Generally, PLDs include a programmable array of cells and array control circuitry which is utilized to program the array with the desired implementation. The programmable array comprises a series of low-voltage, short channel floating gate transistors which store charge to reflect whether a particular cell is programmed with a bit of data. The programmed array reflects in a particular user's individual configuration for the programmable device, allowing users to customize the programmable logic device for a number of different applications.
One type of programmable logic device which has become popular due to its performance and cost characteristics are electrically erasable (E.sup.2) CMOS programmable devices.
Erasable CMOS technology is based on the concept of a stored charge on a floating gate. Electrons are transferred to the gate through a physical mechanism known as Fowler-Nordheim tunneling. For an electrically erasable cell, a tunnel oxide is present between the source and drain regions and the floating gate that is about one-third of the thickness of a traditional transistor gate oxide. Fowler-Nordheim tunneling involves placing a potential across the tunnel oxide which distorts the electric field and allows electrons to traverse the tunnel oxide upon which they become trapped on a floating gate.
The control circuitry of the cell--the program transistors--essentially comprise high voltage transistors capable of sustaining high electric fields. So called read transistors, which operate at low voltage, include a first junction, second junction and gate (defined by the word line of the device). A program junction is separated from the floating gate by an oxide layer having a thickness of approximately 180 .ANG.. The program transistor includes a first junction, second junction and a gate which also rests on the oxide layer. The memory cell will also include a floating gate, separated from the program junction by a tunnel oxide which may be activated by the control gate. The thickness of tunnel oxide is in a range of approximately 80-100 .ANG..
When programming or erasing the device, a voltage is applied between the program and control gate nodes. The direction of the voltage determines whether the cell is erased or programmed. When erasing, the control gate is given a positive voltage and the program node is grounded. When programming, the program node voltage is elevated and the control gate is grounded.
Several alternative designs of memory cells are utilized. Characteristically, in an E.sup.2 CMOS PLD, four types of transistors are required: high voltage P channel, high voltage N channel, low voltage P channel, and low voltage N channel. Techniques for saving mask steps during the formation of these cells are advantageous as each mask savings reduces the cost of the overall device.
The trend of E.sup.2 PLD devices has been toward lower and lower supply voltages. Consequently, this has required a corresponding scaling down of the gate oxide and two different oxide thicknesses for the gate and tunnel oxides. As the gate oxide thicknesses have been scaled down, they have reached and become even thinner than the tunnel oxide on lightly or undoped silicon.
Traditionally, the manufacturing process for implementing all four types of cells requires a large number of sequential process steps. The reduction in processing steps, and specifically masking steps, is an objective of nearly every process engineer. Each savings of a masking step may result in a significant saving in the cost of manufacture of the particular device.
Generally, four separate masking steps were required to complete the formation of the tunnel regions and overlying oxides for the four different types of devices.
U.S. patent application Ser. No. 08/699,401, entitled OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE, discloses a scheme for reducing the number of masks required for forming the transistors from four to three. The benefit of this is the savings of a mask step, but the process contemplates that the thickness of the tunnel region mask and either the n-channel or p-channel high voltage transistor will be the same. In addition, U.S. patent applications entitled AN INTEGRATED CIRCUIT HAVING, AND PROCESS PROVIDING, DIFFERENT OXIDE LAYER THICKNESSES ON A SUBSTRATE and MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE referenced above disclose methods for forming different oxide thicknesses on a semiconductor substrate. In particular, these applications disclose a method for forming a write transistor with a first oxide thickness, a read transistor with a second oxide thickness and a tunnel oxide with a third oxide thickness.
Typically, in forming a the tunnel and gate oxide regions, a separate mask, etch and growth step is required for the tunnel oxide region. Each of these steps adds to the ultimate cost of the device.
In formation of oxides in general, it is generally known that the provision of nitrogen into the silicon substrate prior to forming the oxide by thermal formation in an oxygen atmosphere results in a different growth of oxide between the region overlying the nitrogen deposited region and the region of the substrate where no nitrogen has been deposited. However, where the oxide thicknesses are relatively small, care must be taken not to damage the surface of the silicon substrate, as growth of the oxide will be impaired.
Conventionally, nitrogen may be implanted at a relatively low energy into the substrate. However, implantation can cause a substrate damage which is difficult to anneal out using conventional annealing methods, and compromise the quality of the oxide for small thicknesses.